Invention relates generally to computer-aided design (xe2x80x9cCADxe2x80x9d) of electronic circuits, and more particularly to graphical visualization and exploration of electronic circuit designs specified in hardware description language (xe2x80x9cHDLxe2x80x9d).
Conventional electronic circuit design tools and methodology employ textual and/or graphical entry means to capture design intent, specify circuit behavior, and communicate design intent and behavior, particularly between original circuit designer and other technical personnel, such as design reader, potential user, or other design team members. CAD environments typically provide software-automated entry means to enable communications between designer and computer-implemented tool, i.e., to capture, analyze, or manipulate design data.
Various graphical representation methods are used to facilitate human visualization and communication, such as: logic symbols, block diagrams, process flowcharts, finite state machine transition diagrams, circuit/logic schematics, timing waveform diagrams, etc. Such graphical representations serve as standard methods to illustrate circuit/logic design textbooks, manufacturer data sheets, and engineering design documents.
Although conventional graphical representations serve to illustrate certain design aspects, thereby effectively improving human communication, such graphical representations are, nonetheless, imprecise and informal, and often limited for communicating critical design information. Moreover, prior to widespread use of computer graphics workstations, which have advanced display outputs and input devices, such graphical representations were employed primarily for manual human visualization purposes, i.e., without convenient means to enter design data into computers. In such prior techniques, man-machine communication relied largely on textual specification (e.g., manually-edited netlist files and Boolean logic equations), which were, nonetheless, generally more precise than purely manual techniques.
More recently, as more powerful computational and graphics processing, and software design tools are developed, operational interaction between designer and computer increasingly is accomplished using graphics-based representations. Hence, more sophisticated CAD applications, such as graphical schematic editors, state machine designers, and graphical simulation waveform viewers, are more widely adopted.
Additionally, several related trends are emerging in CAD tool development and AD-centered design methodology. One important trend is general acceptance of simulation as requisite to conventional design verification. As design complexity continues to increase substantially, however, simulation techniques have also improved significantly, evolving to higher abstraction levels, e.g., from relatively simple transistor circuit-level simulation to logic gate-level simulation to register transfer language (RTL)-level simulation.
Furthermore, as recent system chip designs approach or exceed multi-million-gate counts, even relatively more abstract design definitions at the RTL-level may be difficult for designers and tools to manage, particularly since such large designs may be unacceptably detailed and too unwieldy for practical simulation runs. Accordingly, one increasingly popular approach for handling such complex designs is behavioral-level modeling and simulation, which allows designers to define system functionality at an even higher level of behavioral abstraction.
Unfortunately, with conventional design verification or simulation methodologies, textual specification (i.e., languaged-based definition) of prototype circuit under development is commonly employed. Textual specification of circuit design at structural or gate-level is often referred to as a xe2x80x9cnet list.xe2x80x9d At behavioral-level, textual specification is often defined through source code written in one or more Hardware Description Languages (HDL), which is written similarly to conventional software program instructions.
Another conventional trend in electronic design automation (EDA) is the adoption of logic synthesis to generate detailed logic to implement algorithms or finctions. Instead of manually crafting logic circuits to perform functions, a specification of the intended function is described in HDL format (e.g., behaviorally or at RTL level), then supplied to a special software-automated design tools, such as xe2x80x9clogic synthesizerxe2x80x9d or xe2x80x9cdesign compiler,xe2x80x9d which automatically generate detailed logic gates for implementing desired function.
As a consequence of such synthesized or compiled design methodology, certain familiar structural diagrams, such as gate-level schematics, are no longer generated for designer review, debugging, or documentation. Both design-related files (i.e., input, which is behavioral or RTL-level specification; and output, which is structural, gate-level net list, from the logic synthesizer) are text-based. Hence, designers no longer xe2x80x9cdrawxe2x80x9d schematics, with or without CAD-tool assistance. Accordingly, the design may contain no schematic diagrams.
Yet another conventional trend in EDA is the increased use of hardware description languages for specifying designs, as well as related standardization of HDL formats (e.g., Verilog HDL, and VHSIC HDL (VHDL). Such HDL formats enable design specification at varying abstraction levels (e.g., behavioral, RTL, structural, gate, etc.) Along with increased simulation and synthesis, HDL formats have become common way to specify designs. More importantly, the design database is often maintained textually in one or more HDL files.
Because human designers generally communicate more effectively through graphical interfaces rather than textual specifications, there is increased need to employ graphical CAD tools increasingly to facilitate certain areas of design creation and analysis.
Invention resides in system and/or method for graphically browsing and exploring an electronic design, which is specified according to hardware description or similar language, such as verilog HDL or VHDL. Such system or method is implemented using computer-implemented software application which enables designer dynamically to review various design facets. Design methodology uses HDL-based design specification (i.e., xe2x80x9cgoldenxe2x80x9d or master repository file), which may be created by text editing, or generated, at least in part, interactively or automatically, using one or more automated graphical design tools.
Preferably, user dynamically selects design entirely or partially for graphical presentation. Selected presentations are referred to herein as xe2x80x9cviews,xe2x80x9d such that each view is generated dynamically and may involve one or more instances of user-selected design objects, (e.g., components, pins, circuits, logic blocks, interconnects, signal nets, buses, annotating notes, etc.). During browsing of selected views, user may edit design objects or other functional or non-functional aspects thereof, preferably in connectivity-driven manner (i.e., editing is graphically sensitive to associated design connections.) In this interactive manner, presentation views of design are effectively more intuitive and illustrate design data to convey design intent more understandably, particularly for use in design documentation or other user communication.
Optionally, user saves one or more extracted views of design data in graphical design database. Saved views are retrievable for subsequent edit or transfer to other tools, such as for design documentation. Design may include modular or partitioned functional blocks, wherein each block may comprise one or more hierarchical partition levels. Modules or blocks correspond to functionality at specified design abstraction levels, e.g., behavioral, RTL, structural, gate-level, etc.. Further, modules may correspond to multiple coexisting functional abstractions.
Additionally, browsing of design may be accomplished distributedly through local, wide, or other network (e.g., Internet World Wide Web), such that, when extracting views, the viewing workstation may be distinct from the workstation storing the design database. Multiple views may be presented on networked workstations, simultaneously or at different times.
Design modifications to HDL specification file are applied in controlled manner by direct text edits (e.g., create new HDL source code, or modify existing HDL code), or indirect graphical entry (i.e., thereby updating HDL specification.) In such controlled manner, modification entries may automatically accomplish one or more engineering change orders (ECO), whereby specified design operations (e.g., additions, subtractions, modifications, etc.) are applied to saved views to reflect design changes.